1. Field of the Invention
The present invention relates generally to semiconductor devices and particularly to those including a bipolar transistor device configured of transistor cells arranged in a matrix.
2. Description of the Background Art
Power amplifiers for mobile communications currently, widely used include monolithic microwave integrated circuits (MMICs), hybrid integrated circuits (hybrid ICs), multitip modules and the like. These modules have an amplifying element in the form of a GaAs-metal semiconductor field effect transistor (GaAs-MESFET), a high electron mobility transistor (HEMT), a hetero-junction bipolar transistor (HBT) or the like.
Particularly, a hetero-junction bipolar transistor (hereinafter also simply referred to as an HBT) formed on a GaAs substrate, a Si substrate or the like is expected to serve as a future power element for mobile communications as it is more advantageous than conventional field effect transistors (FETs), as described below:
(1) operable by a single power supply as it does not require a negative gate bias voltage;
(2) capable of turning on/off without having an analogue switch on its drain side, as in a Si-metal oxide semiconductor FET (Si-MOSFET); and
(3) having a high output power density, thus capable of providing a defined output if it is reduced in size as compared to FET power amplifiers.
As such features of the HBT attract attention, an HBT power amplifier is also being applied for example to a 2 W-4 W, high-output mobile telephone, such as the European Global System for Mobile Communications (European GSM), a currently most widely used, 900 MHz band mobile telephone system mainly employing a Si-MOSFET.
A power amplifier employs a transistor device generally configured of a plurality of transistor cells arranged on a semiconductor substrate in rows and columns. Hereinafter such a configuration will also be referred to as a multi transistor cell configuration.
FIG. 14 is a circuit diagram showing a configuration of a bipolar transistor device having a multi transistor cell configuration.
With reference to FIG. 14, a plurality of transistor cells Tr11-Trmn arranged in m rows and n columns in effect operate as a single bipolar transistor device TR, wherein m and n are each a natural number.
Corresponding to the rows of transistor cells, local base lines LBL1-LBLm and local collector lines LCL1-LCLm are arranged, respectively. Hereinafter, local base lines LBL1-LBLm and local collector lines LCL1-LCLm will generally be referred to as a local base line LBL and a local collector line LCL, respectively.
Each transistor cell has its base and collector regions electrically coupled with its corresponding row""s local base and collector lines LBL and LCL, respectively.
Local base lines LBL1-LBLm are each electrically coupled with a common base line CBL. On common base line CBL, a bias current Ibs supplied from a bias supply circuit (not shown) is superimposed on an RF signal input to a base terminal Tb.
Local collector lines LCL1-LCLm are each electrically coupled with a common collector line CCL. Furthermore, each transistor cell has its emitter region electrically coupled with a ground voltage Vss to provide a so-called emitter-grounding.
Transistor device TR applied to a power amplifier receives a radio-frequency input (an RF signal input) at base terminal Tb coupled with common base line CBL and outputs an amplified, radio-frequency output (RF signal output) at collector terminal Tc coupled with common collector line CCL.
Corresponding to transistor cells Tr11-Trmn, base ballast resistors Rb11-Rbmn and emitter ballast resistors Re11-Remn are provided, respectively. A ballast resistor is generally used to prevent a bipolar transistor device having a multi transistor cell configuration from having an uneven collector current attributable for example to an uneven heat distribution caused by heat generation.
More specifically, each base ballast resistor and each emitter ballast resistor when their respective transistor cell operates give a negative feedback to a base current and an emitter current, respectively. Thus they act to eliminate a variation in current between transistor cells to provide a uniform current. This can prevent a specific transistor cell from intensively receiving current and thus prevent the transistor from being thermally destroyed.
FIG. 15 is a conceptual view showing a layout of a bipolar transistor device having a multi transistor cell configuration.
FIG. 15 shows a bipolar transistor device TR configured of transistor cells Tr11-Tr67 arranged in six rows and seven columns by way of example. Transistor cells Tr11-Tr67 are grouped into blocks BLK1-BLK3 each formed of two rows of transistor cells.
Corresponding to blocks BLK1-BLK3, local base lines LBL1-LBL3 are arranged, respectively. Each transistor cell has its base region electrically coupled with its corresponding local base line LBL via a base ballast resistor. In FIG. 15, the arrangement of a base ballast resistor Rb12 for transistor cell Tr12 is shown representatively.
Local base lines LBL1-LBL3 are each coupled with common base line CBL. Common base line CBL passes bias current Ibs and also receives an RF signal input.
Each transistor cell has its collector region coupled with a respective one of local collector lines LCL1a and LCL1b to LCL3a and LCL3b provided for their respective rows of transistor cells. Local collector lines LCL1a and LCL1b to LCL3a and LCL3b are each coupled with collector terminal Tc outputting an amplified RF signal.
Similarly, each transistor cell has its emitter region electrically coupled via an emitter ballast resistor (not shown) with common emitter line CEL coupled with ground voltage Vss.
FIGS. 16A and 16B are graphs each showing a distribution of a base current in a bipolar transistor device having a multi transistor cell configuration.
With reference to FIG. 16A, if the FIG. 15 bipolar transistor TR has a small base current, thermal, mutual interference between the blocks and that between the transistor cells only have a small effect and blocks BLK1-BLK3 have their respective base currents Ib1-Ib3 that are substantially uniform and thus provide a standard amount of current I1.
In contrast, as shown in FIG. 16B, if base current in total increases and thermal, mutual interference between the blocks and that between the transistor cells are no longer negligible, the operating temperature of transistor cells closer to the center of the transistor increases higher than that of peripheral transistor cells and the transistor cells with their operating temperature increased thus have an increased collector current.
In the FIG. 15 exemplary layout, base current Ib2 for block BLK2 closer to the center and thus greater in temperature elevation would have an amount of current I3 (wherein I3 greater than  greater than I1) larger than an amount of current I2 of base currents Ib1 and Ib3 for the other blocks (wherein I2 less than I1). Thus a specific block receives an intensive current.
Furthermore even within a single block a transistor cell closer to the center of the block has its operating temperature increased, resulting in a further uneven temperature profile. For example in FIG. 15 transistor cells Tr34 and Tr44 would have an operating temperature that most readily increase.
Thus, an uneven operating-temperature profile results in an uneven base current (or an uneven collector current), which in turn results in an unevenness between the blocks and further develops to a current intensively flowing in a block through a specific transistor cell, and ultimately, approximately more than 90% of the base current (collector current) flowing through the entire transistor device TR would intensively flow to the specific transistor cell.
Such a significantly intensive current results in the transistor cell having a current-amplification rate xcex2 (collector current/base current) significantly reduced due to heat generation. As such, such an intensive current, as seen in the transistor""s Ic (collector current)-Vce (voltage between collector and emitter) characteristic, is observed as a phenomenon with collector current Ic rapidly decreasing as base current Ib increases even if voltage Vce is constant. Such a phenomenon is also referred to as a gain reduction attributed to an intensive current.
FIG. 17 represents an HBT device""s typical Ic-Vce characteristic and load curve in its power amplification operation.
In FIG. 17 the horizontal axis represents collector-emitter voltage Vce of an HBT corresponding to a transistor cell and the vertical axis represents collector current Ic thereof. These Vce-Ic characteristics are plotted in FIG. 17 with base current Ib serving as a parameter.
With reference to FIG. 17, if collector-emitter voltage Vce is increased while a constant base current is applied, collector loss increases and collector current Ic rapidly decreases in a region. Hereinafter such a region with a rapid reduction in collector current Ic will also be referred to as a xe2x80x9ccollapse region.xe2x80x9d
If collector-emitter voltage Vce has a constant level, such a collapse region expands as base current Ib increases.
A load curve CV1 represents a load curve provided at a matched load resistance (50 xcexa9), or when a standard bias is applied, and the load curve has a highly resistive, efficient locus with a bias point Al serving as its center. Thus, power amplification operation can be performed as desired.
In typical mobile telephone systems including Japanese mobile telephone systems a variation in output impedance of an antenna element is not linked directly to a variation in load of a power amplifier and an isolator is thus employed therebetween. In contrast, the GSM application as described above is significantly oriented to miniaturization and reduction in output loss. Accordingly it is not provided with an isolator. As such, depending on a load condition of the antenna, the power amplifier with an HBT applied thereto would have a significantly varying load impedance.
A load curve CV2 represents a load curve provided when a power amplifier has a significantly varying load impedance, as described above. In this case, a significant reflection occurs and the load curve would expand significantly.
If in this case a transistor cell has a base current increased by an uneven operating temperature, the transistor cell would have a reduced margin for load impedance variation that is applied to avoid operation in the collapse region. In other words, for a given load impedance variation a transistor cell having a base current increased by an intensive current would more readily operate in the collapse region.
FIGS. 18A-18C represent an amplification operation of a typical power amplifier in a mobile telephone.
FIG. 18A represents a waveform of a signal input to a power amplifier employed in a mobile telephone. The signal input is a voltage signal in a pulse having an amplitude Vp.
FIG. 18B represents a waveform of an output provided when the power amplifier operates in a standard load condition as represented by the FIG. 17 load curve CV1. In this condition, the power amplifier exhibits a normal amplification characteristic and a pulsed, output signal has a constant power amplification.
FIG. 18C represents a waveform of an output provided when a transistor in the power amplifier operates in a collapse region, as shown in FIG. 17 by load curve CV2. In such a case, while a pulsed signal is amplified a single pulse would have therein a reduction in output power. As such, a pulsed signal input is inaccurately amplified and a single pulse would have therein a variation in output power. This may prevent normal communication.
Thus if a specific transistor cell receives an intensive current attributed to thermal unevenness the entire transistor device might have an impaired amplification characteristic. Furthermore, if such an intensive current is further intensified, not only is an amplification characteristic impaired but the transistor device may be destroyed.
Such disadvantages attributable to intensive current are common among bipolar transistor devices having multi transistor configuration. A GaAs substrate, on which an HBT is formed, has a high thermal resistance and once heat is generated it is hardly released therefrom, readily resulting in a thermally uneven profile across transistor cells. Thus, power amplifiers employing an HBT would more significantly suffer such disadvantages as described above.
Intensive current attributable to thermal unevenness can be prevented to some extent by providing a ballast resistor previously described. If ballast resistors are uniformly provided, however, they hardly effectively reduce an intensive current flowing to a specific block before a specific transistor cell receives an intensive current.
Transistor cells arranged in rows and columns can have a more uniform thermal distribution thereacross if a smaller number of transistor cells are arranged closer to the center of the transistor device and a larger number of transistor cells are arranged closer to the periphery thereof to alleviate heat generation and thermal effect at the center thereof or if ballast resistors closer to the center thereof, which generates heat intensively, are adapted to have a large value of resistance and those closer to the periphery thereof, which is free from significant temperature elevation, are adapted to have a small value of resistance.
Such adjustments, however, require a long period of time to optimize the number of transistor cells and the values in resistance of ballast resistors and they would in effect be hard to achieve.
The present invention contemplates providing a semiconductor device including a bipolar transistor device having a so-called multitransistor configuration with a circuit configuration capable of preventing a specific transistor cell from receiving an intensive current, to enable the transistor device to provide a reliable amplification operation and also to reduce the possibility of the device being destroyed.
Briefly speaking, the semiconductor device includes a plurality of transistor cells, a plurality of first lines, a plurality of second lines, a reference voltage line and a plurality of bias current supply circuits. The plurality of transistor cells are divided and thus arranged in a plurality of blocks to form the bipolar transistor device. The plurality of first lines are provided for the plurality of blocks, respectively, and each electrically coupled with the base region of each transistor cell of the corresponding block. The plurality of second lines are provided for the plurality of blocks, respectively, and each electrically coupled with one of the collector and emitter regions of each transistor cell of the corresponding block. The reference voltage line is electrically coupled with the other of the collector and emitter regions of each of the plurality of transistor cells. The plurality of bias current supply circuits are provided for the plurality of blocks, respectively, and each supplies a bias current to a corresponding one of the plurality of first lines. If the bias current increases, each bias current supply circuit reduces an amount of bias current to be supplied.
Thus a main advantage of the present invention is that by supplying a bias current via a bias current supply circuit arranged individually for each block and capable of giving a negative feedback to an increase in bias current, a bias current for a block receiving an intensive current attributed to thermal unevenness can be controlled to prevent a specific block from receiving an intensive current before a specific transistor cell receives an intensive current. Thus the transistor device can have a steady amplification characteristic and also be free from destruction.
In the present invention in another aspect the semiconductor device includes a plurality of transistor cells, a plurality of first lines, a plurality of second lines, a reference voltage line and a plurality of feedback circuits. The plurality of transistor cells are divided and thus arranged in a plurality of blocks to form the bipolar transistor device. The plurality of first lines are provided for the plurality of blocks, respectively, and each electrically coupled with the base region of each transistor cell of the corresponding block. The plurality of second lines are provided for the plurality of blocks, respectively, and each electrically coupled with one of the collector and emitter regions of each transistor cell of the corresponding block. The reference voltage line is electrically coupled with the other of the collector and emitter regions of each of the plurality of transistor cells. The plurality of feedback circuits are provided for the plurality of blocks, respectively, and each electrically coupling a corresponding one of the plurality of second lines and a predetermined internal node together if the corresponding second line and the internal node have therebetween a voltage difference exceeding a predetermined level of voltage.
Thus, the feedback circuits each arranged for a block of multiple transistor cells can maintain a predetermined level of voltage or less of one of collector and emitter regions that is not coupled with the reference voltage line. As such, each transistor cell can be operated avoiding a region having a gain significantly reduced. Thus, each transistor cell can be free of operation under a severe condition attributable for example to intensive current and the transistor device can thus have a steady amplification characteristic and also be free from destruction.
In the present invention in still another aspect a semiconductor device provided on a semiconductor chip includes a plurality of bipolar transistor devices amplifying a signal in phases. The plurality of bipolar transistor devices are arranged on the semiconductor chip, a bipolar transistor device of a stage preceding another stage arranged at a location experiencing a greater temperature elevation than another location.
As such, of the plurality of transistor devices amplifying a signal in phase, transistor devices of subsequent stages, accommodating higher levels of power and thus readily generating heat, can be successively arranged at locations experiencing lower levels of temperature elevation. As such, if temperature elevation causes intensive current, a transistor device accommodating a high level of power can receive reduced power. This allows each transistor device to provide reliable amplification and can also reduce the possibility of the device being destroyed.
In the present invention in still another aspect a semiconductor device provided on a semiconductor chip includes a plurality of transistor cells, a plurality of first lines, a plurality of second lines, a reference voltage line, a bias current supply circuit, and a plurality of ballast resistors. The plurality of transistor cells are divided and thus arranged in a plurality of blocks to form the bipolar transistor device. The plurality of first lines are provided for the plurality of blocks, respectively, and each electrically coupled with the base region of each transistor cell of the corresponding block. The plurality of second lines are provided for the plurality of blocks, respectively, and each electrically coupled with one of the collector and emitter regions of each transistor cell of the corresponding block. The reference voltage line is electrically coupled with the other of the collector and emitter regions of each of the plurality of transistor cells. The bias supply circuit is shared by the plurality of blocks and supplies each first line with a bias current. The plurality of ballast resistors are provided for the plurality of blocks, respectively, and each electrically coupled between the bias supply circuit and a corresponding one of the plurality of first lines. The plurality of ballast resistors are arranged on the semiconductor chip at a location experiencing a greater temperature elevation than a location having the plurality of transistor cells arranged therein.
For each block of multiple transistor cells configuring the transistor device a ballast resistor can be arranged on the semiconductor chip at a location experiencing a high temperature elevation, to give a negative feedback to an increase of a bias current for a specific block. This can efficiently reduce an intensive current flowing to a specific transistor cell that is attributed to thermal unevenness and the transistor device can thus have a steady amplification characteristic and also be free from destruction.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.